Feijen High-Tech Innovations
FHTI brings you innovation to life

Work history Frans Feijen.

QLTC crisis Project manager, KMWE, 01/07/2018 – 01/01/2019

  • Project manager of 4 short running QLTC projects, running from requirements definition until production startup (IQ/OQ/PQ) in fine mechanical system manufacturing.
  • Typical project scope: lead time 4-6 month’s, costs 0.1- 3 mln €, 6-8/year, 3-8 team members/project  

Bussiness plan developer for Projects & project teams, Ajilon, 01/01/2018 – 01/07/2018

  • Business plan creation for project & Program management for large technical projects in the high-tech industry. (PRODUCTION & INNOVATION).  

Innovation program Manager, NXP, 01/09/2016 UNTIL 01/01/2018

  • Program management for the innovation of a new 5G Cu-pillar flip chip communication package. QLTC responsible.
  • Typical project scope: lead time 12-16month’s, costs 1-6 mln €, 21/year, several global multi-disciplinary teams of 5-7 resources.   

Project manager mechatronic platings systems, BESI, 01/02/2015 - 01/09/2017

  • Project manager of 3 to 6 new solar and semiconductor fine mechanical plating systems per year ranging from 1 to 5 million €.
  • Responsible from design start until release in production (IQ/OQ/PQ) in a world environment.
  • Typical project scope: lead time 9-12 month’s, costs 0.7 - 2 mln €/ line, 4-6/year
  • 3-8 team members/project.  

Technical lead, Liquavista, 01/01/2014 – 01/02/2015

  • On e of 5 technical project team leaders for development of innovative electro wetting display (EWD) production.

  • Multidisiplinary team leader and lead engineer of the pixel wall development team (4 fte.)

LITHOGRAPHIC SR. engineer & project lead, NXP, 01/03/2000 - 01/01/2014   

  •  Green/black belt projects IC industry.
  •  Lithographic group lead (5fte. process and equipment engineers)
  • Project manager and engineer of lithographic capacity, process and equipment improvements for new technologies or factory expansions.
  • Introduced new products and production flows in MEMS, LDMOS, CMOS, HVMOS and LOGIC PROCESSES.
  • Typical project scope: lead time 4-6 month’s, costs 0.3 - 2 mln €/ line, 3-4/year
  • 3-8 team members/project.